Clifford Wolf 0a02cdb93b Fix and_or_buffer optimization in opt_expr for signed operators		2017-07-01 16:05:26 +02:00
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cmds	Add "design -import"	2017-06-30 19:18:52 +02:00
equiv	Fix equiv_simple, old behavior now available with "equiv_simple -short"	2017-04-28 18:57:53 +02:00
fsm	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
hierarchy	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
memory	Typo fix.	2016-09-08 10:57:16 +03:00
opt	Fix and_or_buffer optimization in opt_expr for signed operators	2017-07-01 16:05:26 +02:00
proc	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
sat	Add "setundef -anyseq"	2017-05-28 11:59:05 +02:00
techmap	Fix handling of init values in "abc -dff" and "abc -clk"	2017-06-20 15:32:23 +02:00
tests	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00