riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/examples/intel/DE2i-150
History
Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example) 2017-04-12 16:51:46 +02:00
..
quartus_compile Replace CRLF line endings with LF in de2i.qsf (quartus example) 2017-04-12 16:51:46 +02:00
run_cycloneiv Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
sevenseg.v Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
top.v Squelch trailing whitespace 2017-04-12 15:11:09 +02:00