mirror of https://github.com/YosysHQ/yosys.git
24 lines
421 B
Verilog
24 lines
421 B
Verilog
module gold (input clock, ctrl, din, output reg dout);
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always @(posedge clock) begin
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if (1'b1) begin
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if (1'b0) begin end else begin
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dout <= 0;
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end
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if (ctrl)
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dout <= din;
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end
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end
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endmodule
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module gate (input clock, ctrl, din, output reg dout);
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always @(posedge clock) begin
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if (1'b1) begin
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if (1'b0) begin end else begin
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dout <= 0;
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end
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end
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if (ctrl)
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dout <= din;
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end
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endmodule
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