yosys/docs/source/APPNOTE_011_Design_Investig.../foobaraddsub.v

9 lines
240 B
Verilog

module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
input [7:0] a, b, c, d;
output [7:0] fa, fs, ba, bs;
assign fa = a + (* foo *) b;
assign fs = a - (* foo *) b;
assign ba = c + (* bar *) d;
assign bs = c - (* bar *) d;
endmodule