mirror of https://github.com/YosysHQ/yosys.git
387 lines
11 KiB
C++
387 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "passes/techmap/libparse.h"
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#include "kernel/cost.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct statdata_t
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{
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#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
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X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
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#define STAT_NUMERIC_MEMBERS STAT_INT_MEMBERS X(area)
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#define X(_name) int _name;
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STAT_INT_MEMBERS
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#undef X
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double area;
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string tech;
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std::map<RTLIL::IdString, int> techinfo;
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std::map<RTLIL::IdString, int, RTLIL::sort_by_id_str> num_cells_by_type;
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std::set<RTLIL::IdString> unknown_cell_area;
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statdata_t operator+(const statdata_t &other) const
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{
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statdata_t sum = other;
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#define X(_name) sum._name += _name;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto &it : num_cells_by_type)
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sum.num_cells_by_type[it.first] += it.second;
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return sum;
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}
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statdata_t operator*(int other) const
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{
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statdata_t sum = *this;
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#define X(_name) sum._name *= other;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto &it : sum.num_cells_by_type)
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it.second *= other;
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return sum;
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}
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statdata_t()
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{
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#define X(_name) _name = 0;
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STAT_NUMERIC_MEMBERS
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, double> &cell_area, string techname)
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{
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tech = techname;
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#define X(_name) _name = 0;
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STAT_NUMERIC_MEMBERS
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#undef X
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for (auto wire : mod->selected_wires())
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{
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if (wire->name[0] == '\\') {
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num_pub_wires++;
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num_pub_wire_bits += wire->width;
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}
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num_wires++;
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num_wire_bits += wire->width;
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}
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for (auto &it : mod->memories) {
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if (!design->selected(mod, it.second))
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continue;
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num_memories++;
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num_memory_bits += it.second->width * it.second->size;
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}
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for (auto cell : mod->selected_cells())
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{
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RTLIL::IdString cell_type = cell->type;
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if (width_mode)
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{
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if (cell_type.in(ID($not), ID($pos), ID($neg),
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ID($logic_not), ID($logic_and), ID($logic_or),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
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ID($lut), ID($and), ID($or), ID($xor), ID($xnor),
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ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
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ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
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ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
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int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
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int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
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int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
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cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
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}
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else if (cell_type.in(ID($mux), ID($pmux)))
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
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else if (cell_type.in(
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ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre),
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ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
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ID($dlatch), ID($adlatch), ID($dlatchsr)))
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
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}
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if (!cell_area.empty()) {
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if (cell_area.count(cell_type))
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area += cell_area.at(cell_type);
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else
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unknown_cell_area.insert(cell_type);
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}
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num_cells++;
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num_cells_by_type[cell_type]++;
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}
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for (auto &it : mod->processes) {
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if (!design->selected(mod, it.second))
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continue;
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num_processes++;
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}
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}
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void log_data(RTLIL::IdString mod_name, bool top_mod)
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{
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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log(" Number of public wires: %6d\n", num_pub_wires);
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log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
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log(" Number of memories: %6d\n", num_memories);
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log(" Number of memory bits: %6d\n", num_memory_bits);
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log(" Number of processes: %6d\n", num_processes);
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log(" Number of cells: %6d\n", num_cells);
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for (auto &it : num_cells_by_type)
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if (it.second)
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log(" %-26s %6d\n", log_id(it.first), it.second);
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if (!unknown_cell_area.empty()) {
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log("\n");
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for (auto cell_type : unknown_cell_area)
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log(" Area for cell type %s is unknown!\n", cell_type.c_str());
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}
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if (area != 0) {
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log("\n");
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log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
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}
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if (tech == "xilinx")
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{
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int lut6_cnt = num_cells_by_type[ID(LUT6)];
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int lut5_cnt = num_cells_by_type[ID(LUT5)];
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int lut4_cnt = num_cells_by_type[ID(LUT4)];
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int lut3_cnt = num_cells_by_type[ID(LUT3)];
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int lut2_cnt = num_cells_by_type[ID(LUT2)];
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int lut1_cnt = num_cells_by_type[ID(LUT1)];
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int lc_cnt = 0;
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lc_cnt += lut6_cnt;
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lc_cnt += lut5_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut5_cnt, lut1_cnt);
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lut5_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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lc_cnt += lut4_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut4_cnt, lut1_cnt);
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lut4_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut4_cnt, lut2_cnt);
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lut4_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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lc_cnt += lut3_cnt;
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if (lut1_cnt) {
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int cnt = std::min(lut3_cnt, lut1_cnt);
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lut3_cnt -= cnt;
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lut1_cnt -= cnt;
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}
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if (lut2_cnt) {
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int cnt = std::min(lut3_cnt, lut2_cnt);
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lut3_cnt -= cnt;
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lut2_cnt -= cnt;
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}
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if (lut3_cnt) {
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int cnt = (lut3_cnt + 1) / 2;
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lut3_cnt -= cnt;
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}
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lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
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log("\n");
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log(" Estimated number of LCs: %10d\n", lc_cnt);
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}
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if (tech == "cmos")
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{
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int tran_cnt = 0;
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bool tran_cnt_exact = true;
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auto &gate_costs = CellCosts::cmos_gate_cost();
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for (auto it : num_cells_by_type) {
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auto ctype = it.first;
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auto cnum = it.second;
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if (gate_costs.count(ctype))
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tran_cnt += cnum * gate_costs.at(ctype);
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else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
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tran_cnt += cnum * 16;
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else
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tran_cnt_exact = false;
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}
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log("\n");
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log(" Estimated number of transistors: %10d%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
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}
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}
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};
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statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
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{
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statdata_t mod_data = mod_stat.at(mod);
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std::map<RTLIL::IdString, int, RTLIL::sort_by_id_str> num_cells_by_type;
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num_cells_by_type.swap(mod_data.num_cells_by_type);
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for (auto &it : num_cells_by_type)
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if (mod_stat.count(it.first) > 0) {
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log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, log_id(it.first), it.second);
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mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
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mod_data.num_cells -= it.second;
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} else {
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mod_data.num_cells_by_type[it.first] += it.second;
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}
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return mod_data;
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}
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void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_file)
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{
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std::ifstream f;
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f.open(liberty_file.c_str());
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yosys_input_files.insert(liberty_file);
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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for (auto cell : libparser.ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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cell_area["\\" + cell->args[0]] = atof(ar->value.c_str());
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}
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}
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struct StatPass : public Pass {
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StatPass() : Pass("stat", "print some statistics") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" stat [options] [selection]\n");
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log("\n");
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log("Print some statistics (number of objects) on the selected portion of the\n");
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log("design.\n");
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log("\n");
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log(" -top <module>\n");
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log(" print design hierarchy with this module as top. if the design is fully\n");
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log(" selected and a module has the 'top' attribute set, this module is used\n");
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log(" default value for this option.\n");
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log("\n");
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log(" -liberty <liberty_file>\n");
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log(" use cell area information from the provided liberty file\n");
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log("\n");
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log(" -tech <technology>\n");
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log(" print area estemate for the specified technology. Currently supported\n");
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log(" values for <technology>: xilinx, cmos\n");
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log("\n");
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log(" -width\n");
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log(" annotate internal cell types with their word width.\n");
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log(" e.g. $add_8 for an 8 bit wide $add cell.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Printing statistics.\n");
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bool width_mode = false;
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RTLIL::Module *top_mod = nullptr;
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std::map<RTLIL::IdString, statdata_t> mod_stat;
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dict<IdString, double> cell_area;
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string techname;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-width") {
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width_mode = true;
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continue;
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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read_liberty_cellarea(cell_area, liberty_file);
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continue;
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}
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if (args[argidx] == "-tech" && argidx+1 < args.size()) {
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techname = args[++argidx];
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continue;
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}
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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if (design->module(RTLIL::escape_id(args[argidx+1])) == nullptr)
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log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
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top_mod = design->module(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (techname != "" && techname != "xilinx" && techname != "cmos")
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log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
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for (auto mod : design->selected_modules())
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{
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if (!top_mod && design->full_selection())
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if (mod->get_bool_attribute(ID::top))
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top_mod = mod;
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statdata_t data(design, mod, width_mode, cell_area, techname);
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mod_stat[mod->name] = data;
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log("\n");
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log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
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log("\n");
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data.log_data(mod->name, false);
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}
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if (top_mod != nullptr && GetSize(mod_stat) > 1)
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{
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log("\n");
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log("=== design hierarchy ===\n");
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log("\n");
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log(" %-28s %6d\n", log_id(top_mod->name), 1);
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statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
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log("\n");
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data.log_data(top_mod->name, true);
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}
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log("\n");
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}
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} StatPass;
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PRIVATE_NAMESPACE_END
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