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3d9ff912c2
yosys
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techlibs
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xilinx
History
Clifford Wolf
ff5c61b120
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
..
tests
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.gitignore
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Makefile.inc
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arith_map.v
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brams.txt
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brams_bb.v
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brams_init.py
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brams_map.v
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cells_map.v
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cells_sim.v
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cells_xtra.sh
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cells_xtra.v
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drams.txt
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drams_bb.v
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drams_map.v
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synth_xilinx.cc
…