mirror of https://github.com/YosysHQ/yosys.git
526 lines
18 KiB
TeX
526 lines
18 KiB
TeX
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\section{Yosys by example -- Advanced Synthesis}
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\begin{frame}
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\sectionpage
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\end{frame}
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\begin{frame}{Overview}
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This section contains 4 subsections:
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\begin{itemize}
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\item Using selections
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\item Advanced uses of techmap
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\item Coarse-grain synthesis
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\item Automatic design changes
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\end{itemize}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Using selections}
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\begin{frame}
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\subsectionpage
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\subsectionpagesuffix
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\end{frame}
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\subsubsection{Simple selections}
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\begin{frame}[fragile]{\subsubsecname}
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Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used
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to apply commands only to part of the design. For example:
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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delete # will delete the whole design, but
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delete foobar # will only delete the module foobar.
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\end{lstlisting}
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\bigskip
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The {\tt select} command can be used to create a selection for subsequent
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commands. For example:
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select foobar # select the module foobar
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delete # delete selected objects
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select -clear # reset selection (select whole design)
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\end{lstlisting}
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\end{frame}
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\subsubsection{Selection by object name}
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\begin{frame}[fragile]{\subsubsecname}
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The easiest way to select objects is by object name. This is usually only done
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in synthesis scripts that are hand-tailored for a specific design.
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\bigskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select foobar # select module foobar
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select foo* # select all modules whose names start with foo
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select foo*/bar* # select all objects matching bar* from modules matching foo*
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select */clk # select objects named clk from all modules
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\end{lstlisting}
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\end{frame}
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\subsubsection{Module and design context}
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\begin{frame}[fragile]{\subsubsecname}
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Commands can be executed in {\it module\/} or {\it design\/} context. Until now all
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commands have been executed in design context. The {\tt cd} command can be used
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to switch to module context.
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\bigskip
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In module context all commands only effect the active module. Objects in the module
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are selected without the {\tt <module\_name>/} prefix. For example:
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\bigskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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cd foo # switch to module foo
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delete bar # delete object foo/bar
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cd mycpu # switch to module mycpu
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dump reg_* # print details on all objects whose names start with reg_
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cd .. # switch back to design
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\end{lstlisting}
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\bigskip
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Note: Most synthesis scripts never switch to module context. But it is a very powerful
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tool for interactive design investigation.
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\end{frame}
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\subsubsection{Selecting by object property or type}
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\begin{frame}[fragile]{\subsubsecname}
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Special pattern can be used to select by object property or type. For example:
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\bigskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select w:reg_* # select all wires whose names start with reg_
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select a:foobar # select all objects with the attribute foobar set
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select a:foobar=42 # select all objects with the attribute foobar set to 42
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select A:blabla # select all modules with the attribute blabla set
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select foo/t:$add # select all $add cells from the module foo
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\end{lstlisting}
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\bigskip
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A complete list of this pattern expressions can be found in the command
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reference to the {\tt select} command.
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\end{frame}
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\subsubsection{Combining selection}
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\begin{frame}[fragile]{\subsubsecname}
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When more than one selection expression is used in one statement they are
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pushed on a stack. The final elements on the stack are combined into a union:
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select t:$dff r:WIDTH>1 # all cells of type $dff and/or with a parameter WIDTH > 1
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\end{lstlisting}
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\bigskip
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Special \%-commands can be used to combine the elements on the stack:
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select t:$dff r:WIDTH>1 %i # all cells of type $dff *AND* with a parameter WIDTH > 1
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\end{lstlisting}
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\medskip
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\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)}
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{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\
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{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\
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{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\
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{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\
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\end{block}
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\end{frame}
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\subsubsection{Expanding selections}
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\begin{frame}[fragile]{\subsubsecname}
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Selections of cells and wires can be expanded along connections using {\tt \%}-codes
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for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}).
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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# select all wires that are inputs to $add cells
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select t:$add %ci w:* %i
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\end{lstlisting}
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\bigskip
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Additional constraints such as port names can be specified.
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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# select all wires that connect a "Q" output with a "D" input
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select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i
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# select the multiplexer tree that drives the signal 'state'
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select state %ci*:+$mux,$pmux[A,B,Y]
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\end{lstlisting}
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\bigskip
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See {\tt help select} for full documentation of this expressions.
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\end{frame}
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\subsubsection{Incremental selection}
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\begin{frame}[fragile]{\subsubsecname}
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Sometime a selection can most easily described by a series of add/delete operations.
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The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
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from the current selection instead of overwriting it.
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select -none # start with an empty selection
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select -add reg_* # select a bunch of objects
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select -del reg_42 # but not this one
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select -add state %ci # and add mor stuff
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\end{lstlisting}
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\bigskip
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Within a select expression the token {\tt \%} can be used to push the previous selection
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on the stack.
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select t:$add t:$sub # select all $add and $sub cells
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select % %ci % %d # select only the input wires to those cells
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\end{lstlisting}
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\end{frame}
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\subsubsection{Creating selection variables}
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\begin{frame}[fragile]{\subsubsecname}
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Selections can be stored under a name with the {\tt select -set <name>}
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command. The stored selections can be used in later select expressions
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using the syntax {\tt @<name>}.
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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select -set cone_a state_a %ci*:-$dff # set @cone_a to the input cone of state_a
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select -set cone_b state_b %ci*:-$dff # set @cone_b to the input cone of state_b
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select @cone_a @cone_b %i # select the objects that are in both cones
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\end{lstlisting}
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\bigskip
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Remember that select expressions can also be used directly as arguments to most
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commands. Some commands also except a single select argument to some options.
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In those cases selection variables must be used to capture more complex selections.
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\medskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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dump @cone_a @cone_b
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select -set cone_ab @cone_a @cone_b %i
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show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
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\end{lstlisting}
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\end{frame}
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\begin{frame}[fragile]{\subsubsecname{} -- Example}
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\begin{columns}
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\column[t]{4cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select_01.v}
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\column[t]{7cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select_01.ys}
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\end{columns}
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\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select_01.pdf}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Advanced uses of techmap}
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\begin{frame}
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\subsectionpage
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\subsectionpagesuffix
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\end{frame}
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\subsubsection{Introduction to techmap}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item
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The {\tt techmap} command replaces cells in the design with implementations given
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as verilog code (called ``map files''). It can replace Yosys' internal cell
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types (such as {\tt \$or}) as well as user-defined cell types.
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\medskip\item
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Verilog parameters are used extensively to customize the internal cell types.
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\medskip\item
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Additional special parameters are used by techmap to communicate meta-data to the
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map files.
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\medskip\item
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Special wires are used to instruct techmap how to handle a module in the map file.
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\medskip\item
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Generate blocks and recursion are powerful tools for writing map files.
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example 1/2}
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\vskip-0.2cm
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To map the Verilog OR-reduction operator to 3-input OR gates:
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\vskip-0.2cm
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\begin{columns}
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\column[t]{0.35\linewidth}
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\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
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\column[t]{0.65\linewidth}
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\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example 2/2}
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\vbox to 0cm{
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\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
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\vss
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}
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\begin{columns}
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\column[t]{6cm}
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\column[t]{4cm}
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\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
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\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
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\end{columns}
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\end{frame}
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\subsubsection{Conditional techmap}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item In some cases only cells with certain properties should be substituted.
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\medskip
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\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module
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in the map file for a certain set of parameters.
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\medskip
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\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it
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is non-zero then the module is disabled for this set of parameters.
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\medskip
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\item Example use-cases:
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\begin{itemize}
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\item coarse-grain cell types that only operate on certain bit widths
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\item memory resources for different memory geometries (width, depth, ports, etc.)
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\end{itemize}
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example}
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\vbox to 0cm{
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\vskip-0.5cm
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\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf}
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\vss
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}
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\vskip-0.5cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v}
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\begin{columns}
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\column[t]{6cm}
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\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v}
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\column[t]{4cm}
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\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys}
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\end{columns}
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\end{frame}
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\subsubsection{Scripting in map modules}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
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in the context of the replacement module.
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\medskip
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\item The wire that comes first in alphabetical oder is interpreted as string (must
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be connected to constants) that is executed as script. Then the wire is removed. Repeat.
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\medskip
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\item You can even call techmap recursively!
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\medskip
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\item Example use-cases:
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\begin{itemize}
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\item Using always blocks in map module: call {\tt proc}
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\item Perform expensive optimizations (such as {\tt freduce}) on cells where
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this is known to work well.
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\item Interacting with custom commands.
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\end{itemize}
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\end{itemize}
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\scriptsize
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PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use
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in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules.
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example}
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\vbox to 0cm{
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\vskip4.2cm
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\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
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\vss
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}
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\vskip-0.6cm
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\begin{columns}
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\column[t]{6cm}
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\vskip-0.6cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
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\column[t]{4.2cm}
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\vskip-0.6cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
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\end{columns}
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\end{frame}
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\subsubsection{Handling constant inputs}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
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{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
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input values to cells.
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\medskip
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\item The former contains 1-bits for all constant input bits on the port.
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\medskip
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\item The latter contains the constant bits or undef (x) for non-constant bits.
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\medskip
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\item Example use-cases:
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\begin{itemize}
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\item Converting arithmetic (for example multiply to shift)
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\item Identify constant addresses or enable bits in memory interfaces.
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\end{itemize}
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example}
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\vbox to 0cm{
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\vskip5.2cm
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\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
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\vss
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}
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\vskip-0.6cm
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\begin{columns}
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\column[t]{6cm}
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\vskip-0.4cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
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\column[t]{4.2cm}
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\vskip-0.6cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
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\end{columns}
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\end{frame}
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\subsubsection{Handling shorted inputs}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
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{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
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\medskip
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\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
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number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
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\medskip
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\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
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\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
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\medskip
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\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
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\medskip
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\item Example use-cases:
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\begin{itemize}
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\item Detecting shared clock or control signals in memory interfaces.
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\item In some cases this can be used for for optimization.
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\end{itemize}
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example}
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\vbox to 0cm{
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\vskip4.5cm
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\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
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\vss
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}
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\vskip-0.6cm
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\begin{columns}
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\column[t]{6cm}
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\vskip-0.4cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
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|
\column[t]{4.2cm}
|
|
\vskip-0.6cm
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|
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
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|
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
|
|
\end{columns}
|
|
\end{frame}
|
|
|
|
\subsubsection{Notes on using techmap}
|
|
|
|
\begin{frame}{\subsubsecname}
|
|
\begin{itemize}
|
|
\item Don't use positional cell parameters in map modules.
|
|
\medskip
|
|
\item Don't try to implement basic logic optimization with techmap. \\
|
|
{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)}
|
|
\medskip
|
|
\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid
|
|
collisions with the user-namespace. But always use two underscores or the
|
|
internal consistency checker will trigger on this cells.
|
|
\medskip
|
|
\item Techmap has two major use cases:
|
|
\begin{itemize}
|
|
\item Creating good logic-level representation of arithmetic functions. \\
|
|
This also means using dedicated hardware resources such as half- and full-adder
|
|
cells in ASICS or dedicated carry logic in FPGAs.
|
|
\smallskip
|
|
\item Mapping of coarse-grain resources such as block memory or DSP cells.
|
|
\end{itemize}
|
|
\end{itemize}
|
|
\end{frame}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
|
\subsection{Coarse-grain synthesis}
|
|
|
|
\begin{frame}
|
|
\subsectionpage
|
|
\subsectionpagesuffix
|
|
\end{frame}
|
|
|
|
\subsubsection{TBD}
|
|
|
|
\begin{frame}{\subsubsecname}
|
|
TBD
|
|
\end{frame}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
|
\subsection{Automatic design changes}
|
|
|
|
\begin{frame}
|
|
\subsectionpage
|
|
\subsectionpagesuffix
|
|
\end{frame}
|
|
|
|
\subsubsection{TBD}
|
|
|
|
\begin{frame}{\subsubsecname}
|
|
TBD
|
|
\end{frame}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
|
\subsection{Summary}
|
|
|
|
\begin{frame}{\subsecname}
|
|
\begin{itemize}
|
|
\item TBD
|
|
\item TBD
|
|
\item TBD
|
|
\item TBD
|
|
\end{itemize}
|
|
|
|
\bigskip
|
|
\bigskip
|
|
\begin{center}
|
|
Questions?
|
|
\end{center}
|
|
|
|
\bigskip
|
|
\bigskip
|
|
\begin{center}
|
|
\url{http://www.clifford.at/yosys/}
|
|
\end{center}
|
|
\end{frame}
|
|
|