yosys/frontends/verilog
Zachary Snow 28e99f2b8c fix width of post-increment/decrement expressions 2023-09-18 23:46:06 -04:00
..
.gitignore
Makefile.inc
const2ast.cc
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h
verilog_frontend.cc
verilog_frontend.h
verilog_lexer.l fmt: %t/$time support 2023-08-11 04:46:52 +02:00
verilog_parser.y fix width of post-increment/decrement expressions 2023-09-18 23:46:06 -04:00