Clifford Wolf 3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-12-18 16:01:22 +01:00
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ast	Make return value of $clog2 signed	2018-11-24 18:49:23 +01:00
blif	Merge pull request #591 from hzeller/virtual-override	2018-08-15 14:05:38 +02:00
ilang	read_ilang: allow slicing sigspecs.	2018-12-16 17:53:26 +00:00
json	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
liberty	Allow square brackets in liberty identifiers	2018-11-05 12:33:33 +01:00
verific	Improve src tagging (using names and attrs) of cells and wires in verific front-end	2018-12-18 16:01:22 +01:00
verilog	verilog_parser: Properly handle recursion when processing attributes	2018-12-14 12:48:00 +01:00