mirror of https://github.com/YosysHQ/yosys.git
283 lines
9.7 KiB
C++
283 lines
9.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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// defined in proc_clean.cc
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extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
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static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
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{
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if (signal.size() != 1)
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return false;
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if (signal == ref)
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return true;
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for (auto cell : mod->cells())
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{
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if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
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polarity = !polarity;
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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}
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if (cell->type == "$not" && cell->get("\\Y") == signal) {
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polarity = !polarity;
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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}
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if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
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if (cell->get("\\A").is_fully_const()) {
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if (!cell->get("\\A").as_bool())
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polarity = !polarity;
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return check_signal(mod, cell->get("\\B"), ref, polarity);
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}
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if (cell->get("\\B").is_fully_const()) {
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if (!cell->get("\\B").as_bool())
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polarity = !polarity;
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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}
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}
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if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
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if (cell->get("\\A").is_fully_const()) {
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if (cell->get("\\A").as_bool())
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polarity = !polarity;
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return check_signal(mod, cell->get("\\B"), ref, polarity);
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}
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if (cell->get("\\B").is_fully_const()) {
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if (cell->get("\\B").as_bool())
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polarity = !polarity;
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return check_signal(mod, cell->get("\\A"), ref, polarity);
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}
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}
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}
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return false;
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}
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static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::SigSpec &rval, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity, bool unknown)
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{
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for (auto &action : cs->actions) {
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if (unknown)
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rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval);
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else
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rspec.replace(action.first, action.second, &rval);
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}
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for (auto sw : cs->switches) {
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if (sw->signal.size() == 0) {
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for (auto cs2 : sw->cases)
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apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown);
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}
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bool this_polarity = polarity;
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if (check_signal(mod, sw->signal, const_sig, this_polarity)) {
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for (auto cs2 : sw->cases) {
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for (auto comp : cs2->compare)
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if (comp == RTLIL::SigSpec(this_polarity, 1))
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goto matched_case;
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if (cs2->compare.size() == 0) {
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matched_case:
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apply_const(mod, rspec, rval, cs2, const_sig, polarity, false);
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break;
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}
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}
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} else {
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for (auto cs2 : sw->cases)
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apply_const(mod, rspec, rval, cs2, const_sig, polarity, true);
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}
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}
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}
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static void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity)
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{
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for (auto sw : cs->switches) {
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bool this_polarity = polarity;
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if (check_signal(mod, sw->signal, const_sig, this_polarity)) {
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bool found_rem_path = false;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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for (auto comp : cs2->compare)
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if (comp == RTLIL::SigSpec(this_polarity, 1))
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goto matched_case;
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if (found_rem_path) {
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matched_case:
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sw->cases.erase(sw->cases.begin() + (i--));
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delete cs2;
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continue;
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}
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found_rem_path = true;
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cs2->compare.clear();
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}
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sw->signal = RTLIL::SigSpec();
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} else {
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for (auto cs2 : sw->cases)
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eliminate_const(mod, cs2, const_sig, polarity);
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}
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}
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int dummy_count = 0;
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bool did_something = true;
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while (did_something) {
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did_something = false;
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proc_clean_case(cs, did_something, dummy_count, 1);
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}
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}
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static void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
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{
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restart_proc_arst:
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if (proc->root_case.switches.size() != 1)
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return;
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RTLIL::SigSpec root_sig = proc->root_case.switches[0]->signal;
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for (auto &sync : proc->syncs) {
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
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bool polarity = sync->type == RTLIL::SyncType::STp;
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if (check_signal(mod, root_sig, sync->signal, polarity)) {
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if (proc->syncs.size() == 1) {
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log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
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} else {
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log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
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sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0;
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}
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for (auto &action : sync->actions) {
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RTLIL::SigSpec rspec = action.second;
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RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
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for (int i = 0; i < SIZE(rspec); i++)
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if (rspec[i].wire == NULL)
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rval[i] = rspec[i];
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RTLIL::SigSpec last_rval;
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for (int count = 0; rval != last_rval; count++) {
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last_rval = rval;
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apply_const(mod, rspec, rval, &proc->root_case, root_sig, polarity, false);
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assign_map.apply(rval);
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if (rval.is_fully_const())
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break;
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if (count > 100)
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log_error("Async reset %s yields endless loop at value %s for signal %s.\n",
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log_signal(sync->signal), log_signal(rval), log_signal(action.first));
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rspec = rval;
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}
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if (rval.has_marked_bits())
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log_error("Async reset %s yields non-constant value %s for signal %s.\n",
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log_signal(sync->signal), log_signal(rval), log_signal(action.first));
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action.second = rval;
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}
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eliminate_const(mod, &proc->root_case, root_sig, polarity);
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goto restart_proc_arst;
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}
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}
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}
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}
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struct ProcArstPass : public Pass {
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ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_arst [-global_arst [!]<netname>] [selection]\n");
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log("\n");
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log("This pass identifies asynchronous resets in the processes and converts them\n");
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log("to a different internal representation that is suitable for generating\n");
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log("flip-flop cells with asynchronous resets.\n");
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log("\n");
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log(" -global_arst [!]<netname>\n");
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log(" In modules that have a net with the given name, use this net as async\n");
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log(" reset for registers that have been assign initial values in their\n");
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log(" declaration ('reg foobar = constant_value;'). Use the '!' modifier for\n");
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log(" active low reset signals. Note: the frontend stores the default value\n");
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log(" in the 'init' attribute on the net.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string global_arst;
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bool global_arst_neg = false;
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log_header("Executing PROC_ARST pass (detect async resets in processes).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-global_arst" && argidx+1 < args.size()) {
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global_arst = args[++argidx];
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if (!global_arst.empty() && global_arst[0] == '!') {
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global_arst_neg = true;
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global_arst = global_arst.substr(1);
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}
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global_arst = RTLIL::escape_id(global_arst);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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SigMap assign_map(mod);
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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proc_arst(mod, proc_it.second, assign_map);
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if (global_arst.empty() || mod->wire(global_arst) == nullptr)
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continue;
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std::vector<RTLIL::SigSig> arst_actions;
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for (auto sync : proc_it.second->syncs)
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
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for (auto &act : sync->actions) {
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RTLIL::SigSpec arst_sig, arst_val;
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for (auto &chunk : act.first.chunks())
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if (chunk.wire && chunk.wire->attributes.count("\\init")) {
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RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
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value.extend(chunk.wire->width, false);
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arst_sig.append(chunk);
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arst_val.append(value.extract(chunk.offset, chunk.width));
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}
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if (arst_sig.size()) {
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log("Added global reset to process %s: %s <- %s\n",
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proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val));
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arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
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}
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}
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if (!arst_actions.empty()) {
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RTLIL::SyncRule *sync = new RTLIL::SyncRule;
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sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
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sync->signal = mod->wire(global_arst);
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sync->actions = arst_actions;
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proc_it.second->syncs.push_back(sync);
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}
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}
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}
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}
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} ProcArstPass;
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