This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
3c41599ee1
yosys
/
tests
/
ecp5
/
tribuf.v
9 lines
108 B
Verilog
Raw
Blame
History
module
tristate
(
en
,
i
,
o
)
;
input
en
;
input
i
;
output
o
;
assign
o
=
en
?
i
:
1
'
bz
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink