mirror of https://github.com/YosysHQ/yosys.git
107 lines
3.8 KiB
Verilog
107 lines
3.8 KiB
Verilog
module EFX_LUT4(
|
|
output O,
|
|
input I0,
|
|
input I1,
|
|
input I2,
|
|
input I3
|
|
);
|
|
parameter LUTMASK = 16'h0000;
|
|
endmodule
|
|
|
|
module EFX_ADD(
|
|
output O,
|
|
output CO,
|
|
input I0,
|
|
input I1,
|
|
input CI
|
|
);
|
|
parameter I0_POLARITY = 1;
|
|
parameter I1_POLARITY = 1;
|
|
endmodule
|
|
|
|
module EFX_FF(
|
|
output Q,
|
|
input D,
|
|
input CE,
|
|
input CLK,
|
|
input SR
|
|
);
|
|
parameter CLK_POLARITY = 1;
|
|
parameter CE_POLARITY = 1;
|
|
parameter SR_POLARITY = 1;
|
|
parameter SR_SYNC = 0;
|
|
parameter SR_VALUE = 0;
|
|
parameter SR_SYNC_PRIORITY = 0;
|
|
parameter D_POLARITY = 1;
|
|
endmodule
|
|
|
|
module EFX_GBUFCE(
|
|
input CE,
|
|
input I,
|
|
output O
|
|
);
|
|
parameter CE_POLARITY = 1'b1;
|
|
endmodule
|
|
|
|
module EFX_RAM_5K(
|
|
input [WRITE_WIDTH-1:0] WDATA,
|
|
input [WRITE_ADDR_WIDTH-1:0] WADDR,
|
|
input WE,
|
|
input WCLK,
|
|
input WCLKE,
|
|
output [READ_WIDTH-1:0] RDATA,
|
|
input [READ_ADDR_WIDTH-1:0] RADDR,
|
|
input RE,
|
|
input RCLK
|
|
);
|
|
parameter READ_WIDTH = 20;
|
|
parameter WRITE_WIDTH = 20;
|
|
parameter OUTPUT_REG = 1'b0;
|
|
parameter RCLK_POLARITY = 1'b1;
|
|
parameter RE_POLARITY = 1'b1;
|
|
parameter WCLK_POLARITY = 1'b1;
|
|
parameter WE_POLARITY = 1'b1;
|
|
parameter WCLKE_POLARITY = 1'b1;
|
|
parameter WRITE_MODE = "READ_FIRST";
|
|
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
|
|
localparam READ_ADDR_WIDTH =
|
|
(READ_WIDTH == 16) ? 8 : // 256x16
|
|
(READ_WIDTH == 8) ? 9 : // 512x8
|
|
(READ_WIDTH == 4) ? 10 : // 1024x4
|
|
(READ_WIDTH == 2) ? 11 : // 2048x2
|
|
(READ_WIDTH == 1) ? 12 : // 4096x1
|
|
(READ_WIDTH == 20) ? 8 : // 256x20
|
|
(READ_WIDTH == 10) ? 9 : // 512x10
|
|
(READ_WIDTH == 5) ? 10 : -1; // 1024x5
|
|
|
|
localparam WRITE_ADDR_WIDTH =
|
|
(WRITE_WIDTH == 16) ? 8 : // 256x16
|
|
(WRITE_WIDTH == 8) ? 9 : // 512x8
|
|
(WRITE_WIDTH == 4) ? 10 : // 1024x4
|
|
(WRITE_WIDTH == 2) ? 11 : // 2048x2
|
|
(WRITE_WIDTH == 1) ? 12 : // 4096x1
|
|
(WRITE_WIDTH == 20) ? 8 : // 256x20
|
|
(WRITE_WIDTH == 10) ? 9 : // 512x10
|
|
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
|
|
|
|
endmodule |