mirror of https://github.com/YosysHQ/yosys.git
82 lines
1.5 KiB
Verilog
82 lines
1.5 KiB
Verilog
module testbench;
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reg clk;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 clk = 0;
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repeat (10000) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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end
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reg [7:0] data_a = 0;
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reg [7:0] addr_a = 0;
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reg [7:0] addr_b = 0;
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reg we_a = 0;
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reg re_a = 1;
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wire [7:0] q_a;
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reg mem_init = 0;
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reg [7:0] pq_a;
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always @(posedge clk) begin
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#3;
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data_a <= data_a + 17;
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addr_a <= addr_a + 1;
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addr_b <= addr_b + 1;
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end
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always @(posedge addr_a) begin
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#10;
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if(addr_a > 6'h3E)
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mem_init <= 1;
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end
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always @(posedge clk) begin
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//#3;
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we_a <= !we_a;
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end
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reg [7:0] mem [(1<<8)-1:0];
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always @(posedge clk) // Write memory.
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begin
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if (we_a)
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mem[addr_a] <= data_a; // Using write address bus.
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end
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always @(posedge clk) // Read memory.
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begin
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pq_a <= mem[addr_b]; // Using read address bus.
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end
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top uut (
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.din(data_a),
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.write_en(we_a),
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.waddr(addr_a),
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.wclk(clk),
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.raddr(addr_b),
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.rclk(clk),
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.dout(q_a)
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);
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uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a));
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endmodule
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module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B);
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always @(posedge clk)
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begin
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#1;
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if (en == 1 & init == 1 & A !== B)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
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$stop;
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end
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end
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endmodule
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