yosys/backends
Eddie Hung 5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
..
aiger Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
blif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
btor Change "ne" to "neq" in btor2 output 2019-04-19 21:17:12 +02:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Re-indent firrtl.cc:struct memory - no functional change. 2019-05-01 16:21:13 -07:00
ilang Fix a syntax bug in ilang backend related to process case statements 2019-03-14 17:50:20 +01:00
intersynth Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
json Revert "write_json to not write contents (cells/wires) of whiteboxes" 2019-04-18 23:05:59 -07:00
protobuf Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
simplec Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smt2 Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
smv Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog Add support for zero-width signals to Verilog back-end, fixes #948 2019-04-22 19:44:42 +02:00