mirror of https://github.com/YosysHQ/yosys.git
359 lines
11 KiB
C++
359 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivSimpleWorker
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{
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Module *module;
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const vector<Cell*> &equiv_cells;
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Cell *equiv_cell;
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SigMap &sigmap;
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dict<SigBit, Cell*> &bit2driver;
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ezSatPtr ez;
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SatGen satgen;
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int max_seq;
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bool verbose;
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pool<pair<Cell*, int>> imported_cells_cache;
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EquivSimpleWorker(const vector<Cell*> &equiv_cells, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose, bool model_undef) :
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module(equiv_cells.front()->module), equiv_cells(equiv_cells), equiv_cell(nullptr),
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sigmap(sigmap), bit2driver(bit2driver), satgen(ez.get(), &sigmap), max_seq(max_seq), verbose(verbose)
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{
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satgen.model_undef = model_undef;
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}
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bool find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, pool<SigBit> *input_bits, Cell *cell)
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{
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if (cells_cone.count(cell))
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return false;
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cells_cone.insert(cell);
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if (cells_stop.count(cell))
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return true;
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : sigmap(conn.second)) {
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if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_")) {
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if (!conn.first.in("\\CLK", "\\C"))
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next_seed.insert(bit);
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} else
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find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
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}
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return false;
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}
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void find_input_cone(pool<SigBit> &next_seed, pool<Cell*> &cells_cone, pool<SigBit> &bits_cone, const pool<Cell*> &cells_stop, const pool<SigBit> &bits_stop, pool<SigBit> *input_bits, SigBit bit)
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{
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if (bits_cone.count(bit))
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return;
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bits_cone.insert(bit);
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if (bits_stop.count(bit)) {
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if (input_bits != nullptr) input_bits->insert(bit);
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return;
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}
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if (!bit2driver.count(bit))
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return;
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if (find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit2driver.at(bit)))
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if (input_bits != nullptr) input_bits->insert(bit);
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}
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bool run_cell()
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{
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SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
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SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
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int ez_context = ez->frozen_literal();
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if (satgen.model_undef)
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{
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importDefSigBit(bit_b, max_seq+1);
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int ez_undef_a = satgen.importUndefSigBit(bit_a, max_seq+1);
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ez->assume(ez->XOR(ez_a, ez_b), ez_context);
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ez->assume(ez->NOT(ez_undef_a), ez_context);
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}
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else
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{
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int ez_a = satgen.importSigBit(bit_a, max_seq+1);
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int ez_b = satgen.importSigBit(bit_b, max_seq+1);
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ez->assume(ez->XOR(ez_a, ez_b), ez_context);
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}
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pool<SigBit> seed_a = { bit_a };
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pool<SigBit> seed_b = { bit_b };
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if (verbose) {
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log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell));
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log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y")));
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} else {
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log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y")));
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}
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int step = max_seq;
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while (1)
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{
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pool<Cell*> no_stop_cells;
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pool<SigBit> no_stop_bits;
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pool<Cell*> full_cells_cone_a, full_cells_cone_b;
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pool<SigBit> full_bits_cone_a, full_bits_cone_b;
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pool<SigBit> next_seed_a, next_seed_b;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
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next_seed_a.clear();
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
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next_seed_b.clear();
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pool<Cell*> short_cells_cone_a, short_cells_cone_b;
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pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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pool<SigBit> input_bits;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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next_seed_a.swap(seed_a);
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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next_seed_b.swap(seed_b);
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pool<Cell*> problem_cells;
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problem_cells.insert(short_cells_cone_a.begin(), short_cells_cone_a.end());
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problem_cells.insert(short_cells_cone_b.begin(), short_cells_cone_b.end());
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if (verbose)
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log(" Adding %d new cells to the problem (%d A, %d B, %d shared).\n",
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GetSize(problem_cells), GetSize(short_cells_cone_a), GetSize(short_cells_cone_b),
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(GetSize(short_cells_cone_a) + GetSize(short_cells_cone_b)) - GetSize(problem_cells));
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for (auto cell : problem_cells) {
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auto key = pair<Cell*, int>(cell, step+1);
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if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1))
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log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
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imported_cells_cache.insert(key);
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}
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if (satgen.model_undef) {
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for (auto bit : input_bits)
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ez->assume(ez->NOT(satgen.importUndefSigBit(bit, step+1)));
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}
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if (verbose)
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log(" Problem size at t=%d: %d literals, %d clauses\n", step, ez->numCnfVariables(), ez->numCnfClauses());
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if (!ez->solve(ez_context)) {
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log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
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equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
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ez->assume(ez->NOT(ez_context));
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return true;
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}
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if (verbose)
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log(" Failed to prove equivalence with sequence length %d.\n", max_seq - step);
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if (--step < 0) {
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if (verbose)
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log(" Reached sequence limit.\n");
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break;
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}
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if (seed_a.empty() && seed_b.empty()) {
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if (verbose)
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log(" No nets to continue in previous time step.\n");
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break;
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}
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if (seed_a.empty()) {
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if (verbose)
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log(" No nets on A-side to continue in previous time step.\n");
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break;
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}
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if (seed_b.empty()) {
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if (verbose)
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log(" No nets on B-side to continue in previous time step.\n");
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break;
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}
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if (verbose) {
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#if 0
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log(" Continuing analysis in previous time step with the following nets:\n");
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for (auto bit : seed_a)
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log(" A: %s\n", log_signal(bit));
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for (auto bit : seed_b)
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log(" B: %s\n", log_signal(bit));
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#else
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log(" Continuing analysis in previous time step with %d A- and %d B-nets.\n", GetSize(seed_a), GetSize(seed_b));
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#endif
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}
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}
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if (!verbose)
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log(" failed.\n");
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ez->assume(ez->NOT(ez_context));
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return false;
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}
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int run()
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{
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if (GetSize(equiv_cells) > 1) {
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SigSpec sig;
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for (auto c : equiv_cells)
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sig.append(sigmap(c->getPort("\\Y")));
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log(" Grouping SAT models for %s:\n", log_signal(sig));
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}
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int counter = 0;
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for (auto c : equiv_cells) {
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equiv_cell = c;
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if (run_cell())
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counter++;
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}
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return counter;
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}
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};
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struct EquivSimplePass : public Pass {
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EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_simple [options] [selection]\n");
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log("\n");
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log("This command tries to prove $equiv cells using a simple direct SAT approach.\n");
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log("\n");
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log(" -v\n");
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log(" verbose output\n");
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log("\n");
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log(" -undef\n");
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log(" enable modelling of undef states\n");
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log("\n");
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log(" -nogroup\n");
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log(" disabling grouping of $equiv cells by output wire\n");
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log("\n");
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log(" -seq <N>\n");
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log(" the max. number of time steps to be considered (default = 1)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool verbose = false, model_undef = false, nogroup = false;
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int success_counter = 0;
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int max_seq = 1;
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log_header(design, "Executing EQUIV_SIMPLE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-v") {
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verbose = true;
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continue;
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}
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if (args[argidx] == "-undef") {
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model_undef = true;
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continue;
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}
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if (args[argidx] == "-nogroup") {
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nogroup = true;
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continue;
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}
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if (args[argidx] == "-seq" && argidx+1 < args.size()) {
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max_seq = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, Cell*> bit2driver;
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dict<SigBit, dict<SigBit, Cell*>> unproven_equiv_cells;
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int unproven_cells_counter = 0;
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for (auto cell : module->selected_cells())
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if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
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auto bit = sigmap(cell->getPort("\\Y").as_bit());
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auto bit_group = bit;
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if (!nogroup && bit_group.wire)
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bit_group.offset = 0;
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unproven_equiv_cells[bit_group][bit] = cell;
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unproven_cells_counter++;
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}
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if (unproven_equiv_cells.empty())
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continue;
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log("Found %d unproven $equiv cells (%d groups) in %s:\n",
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unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
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for (auto cell : module->cells()) {
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if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_"))
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continue;
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_output(cell->type, conn.first))
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for (auto bit : sigmap(conn.second))
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bit2driver[bit] = cell;
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}
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unproven_equiv_cells.sort();
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for (auto it : unproven_equiv_cells)
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{
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it.second.sort();
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vector<Cell*> cells;
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for (auto it2 : it.second)
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cells.push_back(it2.second);
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EquivSimpleWorker worker(cells, sigmap, bit2driver, max_seq, verbose, model_undef);
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success_counter += worker.run();
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}
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}
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log("Proved %d previously unproven $equiv cells.\n", success_counter);
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}
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} EquivSimplePass;
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PRIVATE_NAMESPACE_END
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