yosys/passes
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
..
cmds Merge pull request #625 from aman-goel/master 2018-09-14 12:36:13 +02:00
equiv stop check_signal_in_fanout from traversing FFs 2018-10-13 23:24:24 +08:00
fsm Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
hierarchy Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
memory memory_bram: Reset make_outreg when growing read ports 2018-10-19 14:46:31 +01:00
opt Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
proc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
sat Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
techmap Merge pull request #591 from hzeller/virtual-override 2018-08-15 14:05:38 +02:00
tests Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00