mirror of https://github.com/YosysHQ/yosys.git
152 lines
2.7 KiB
Plaintext
152 lines
2.7 KiB
Plaintext
# Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules.
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bram $__XILINX_RAMB36_SDP
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init 1
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abits 9
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dbits 72
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 8
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_SDP
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init 1
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abits 9
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dbits 36
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 4
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_TDP
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init 1
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abits 10 @a10d36
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dbits 36 @a10d36
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abits 11 @a11d18
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dbits 18 @a11d18
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abits 12 @a12d9
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dbits 9 @a12d9
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abits 13 @a13d4
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dbits 4 @a13d4
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abits 14 @a14d2
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dbits 2 @a14d2
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abits 15 @a15d1
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dbits 1 @a15d1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 4 @a10d36
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enable 1 2 @a11d18
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enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP
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init 1
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abits 10 @a10d18
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dbits 18 @a10d18
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abits 11 @a11d9
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dbits 9 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 2 @a10d18
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enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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# The "min bits" value were taken from:
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# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
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# v1.14 ed., p 29-30, July, 2019.
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# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
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match $__XILINX_RAMB36_SDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB36_SDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB36_TDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB36_TDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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endmatch
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