mirror of https://github.com/YosysHQ/yosys.git
131 lines
3.8 KiB
C++
131 lines
3.8 KiB
C++
// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include <string>
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#include <map>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// this function is called for each module in the design
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static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits)
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{
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// use a SigMap to convert nets to a unique representation
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SigMap sigmap(module);
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// count how many times a single-bit signal is used
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std::map<RTLIL::SigBit, int> bit_usage_count;
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// count output lines for this module (needed only for summary output at the end)
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int line_count = 0;
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log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
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// For all ports on all cells
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for (auto &cell_iter : module->cells_)
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for (auto &conn : cell_iter.second->connections())
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{
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// Get the signals on the port
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// (use sigmap to get a uniqe signal name)
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RTLIL::SigSpec sig = sigmap(conn.second);
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// add each bit to bit_usage_count, unless it is a constant
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for (auto &bit : sig)
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if (bit.wire != NULL)
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bit_usage_count[bit]++;
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}
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// for each wire in the module
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for (auto &wire_iter : module->wires_)
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{
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RTLIL::Wire *wire = wire_iter.second;
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// .. but only selected wires
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if (!design->selected(module, wire))
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continue;
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// add +1 usage if this wire actually is a port
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int usage_offset = wire->port_id > 0 ? 1 : 0;
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// we will record which bits of the (possibly multi-bit) wire are stub signals
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std::set<int> stub_bits;
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// get a signal description for this wire and split it into separate bits
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RTLIL::SigSpec sig = sigmap(wire);
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// for each bit (unless it is a constant):
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// check if it is used at least two times and add to stub_bits otherwise
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for (int i = 0; i < GetSize(sig); i++)
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if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
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stub_bits.insert(i);
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// continue if no stub bits found
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if (stub_bits.size() == 0)
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continue;
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// report stub bits and/or stub wires, don't report single bits
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// if called with report_bits set to false.
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if (GetSize(stub_bits) == GetSize(sig)) {
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log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
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} else {
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if (!report_bits)
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continue;
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log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
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for (int bit : stub_bits)
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log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
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log("]\n");
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}
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// we have outputted a line, increment summary counter
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line_count++;
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}
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// report summary
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if (report_bits)
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log(" found %d stub wires or wires with stub bits.\n", line_count);
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else
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log(" found %d stub wires.\n", line_count);
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}
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// each pass contains a singleton object that is derived from Pass
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struct StubnetsPass : public Pass {
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StubnetsPass() : Pass("stubnets") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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// variables to mirror information from passed options
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bool report_bits = 0;
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log_header("Executing STUBNETS pass (find stub nets).\n");
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// parse options
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-report_bits") {
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report_bits = true;
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continue;
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}
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break;
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}
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// handle extra options (e.g. selection)
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extra_args(args, argidx, design);
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// call find_stub_nets() for each module that is either
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// selected as a whole or contains selected objects.
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for (auto &it : design->modules_)
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if (design->selected_module(it.first))
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find_stub_nets(design, it.second, report_bits);
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}
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} StubnetsPass;
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PRIVATE_NAMESPACE_END
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