mirror of https://github.com/YosysHQ/yosys.git
13 lines
617 B
Plaintext
13 lines
617 B
Plaintext
read_verilog adffs.v
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proc
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async2sync
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synth -flatten -run coarse # technology-independent coarse grained synthesis
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:SB_DFF
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select -assert-count 1 t:SB_DFFE
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select -assert-count 4 t:SB_LUT4
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#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
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write_verilog adffs_synth.v
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