yosys/tests/sva/sva_value_change_changed.sv

18 lines
206 B
Systemverilog

module top (
input clk,
input a, b
);
default clocking @(posedge clk); endclocking
assert property (
$changed(b)
);
`ifndef FAIL
assume property (
b !== 'x ##1 $changed(b)
);
`endif
endmodule