mirror of https://github.com/YosysHQ/yosys.git
68 lines
1.2 KiB
Plaintext
68 lines
1.2 KiB
Plaintext
read_verilog xilinx_srl.v
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design -save read
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design -copy-to model $__XILINX_SHREG_
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hierarchy -top xilinx_srl_static_test
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prep
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design -save gold
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techmap
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xilinx_srl -fixed
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opt
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# stat
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# show -width
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 2 t:$__XILINX_SHREG_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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dump gate
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sat -verify -prove-asserts -show-ports -seq 5 miter
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#design -load gold
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#stat
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#design -load gate
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#stat
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##########
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design -load read
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design -copy-to model $__XILINX_SHREG_
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hierarchy -top xilinx_srl_variable_test
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prep
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design -save gold
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xilinx_srl -variable
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opt
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#stat
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# show -width
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# write_verilog -noexpr -norename
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select -assert-count 1 t:$dff
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select -assert-count 1 t:$dff r:WIDTH=1 %i
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select -assert-count 2 t:$__XILINX_SHREG_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 5 miter
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# design -load gold
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# stat
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# design -load gate
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# stat
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