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16 lines
408 B
Plaintext
16 lines
408 B
Plaintext
read_verilog latches.v
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proc
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flatten
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equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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async2sync
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equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load preopt
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synth_xilinx
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cd top
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select -assert-count 1 t:LUT1
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select -assert-count 2 t:LUT3
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select -assert-count 3 t:LDCE
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select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D
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