mirror of https://github.com/YosysHQ/yosys.git
23 lines
447 B
Plaintext
23 lines
447 B
Plaintext
|
|
read_verilog <<EOT
|
|
module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
|
|
assign o = (i << 4) + j;
|
|
endmodule
|
|
EOT
|
|
|
|
hierarchy -top wreduce_add_test
|
|
proc
|
|
design -save gold
|
|
|
|
prep
|
|
|
|
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
|
|
|
|
design -stash gate
|
|
|
|
design -import gold -as gold
|
|
design -import gate -as gate
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
sat -verify -prove-asserts -show-ports miter
|