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yosys/frontends/verilog
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Clifford Wolf df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
const2ast.cc initial import 2013-01-05 11:13:26 +01:00
lexer.l initial import 2013-01-05 11:13:26 +01:00
parser.y Tiny fixes to verilog parser 2013-03-23 18:54:31 +01:00
preproc.cc initial import 2013-01-05 11:13:26 +01:00
verilog_frontend.cc Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
verilog_frontend.h initial import 2013-01-05 11:13:26 +01:00