mirror of https://github.com/YosysHQ/yosys.git
56 lines
1.0 KiB
Plaintext
56 lines
1.0 KiB
Plaintext
read_verilog abc9.v
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design -save read
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hierarchy -top abc9_test027
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proc
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design -save gold
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abc9 -lut 4
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check
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top abc9_test028
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proc
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abc9 -lut 4
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select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
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select -assert-count 1 t:unknown
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select -assert-none t:$lut t:unknown %% t: %D
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design -load read
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hierarchy -top abc9_test032
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proc
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clk2fflogic
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design -save gold
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abc9 -lut 4
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check
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -seq 10 -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog -icells <<EOT
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module abc9_test036(input clk, d, output q);
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(* keep *) reg w;
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$__ABC9_FF_ ff(.D(d), .Q(w));
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wire \ff.clock = clk;
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wire \ff.init = 1'b0;
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assign q = w;
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endmodule
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EOT
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abc9 -lut 4 -dff
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