yosys/techlibs
Sylvain Munaut 4f9183d107 ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-05-13 12:51:06 +02:00
..
achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
common Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
coolrunner2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Add handling of init attributes in "opt_expr -undriven" 2019-04-30 14:46:12 +02:00
gowin Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC 2019-05-13 12:51:06 +02:00
intel Fix formatting for synth_intel.cc 2019-05-09 08:40:05 -07:00
sf2 Add link to SF2 / igloo2 macro library guide 2019-03-07 09:08:26 -08:00
xilinx Add "stat -tech xilinx" 2019-05-11 09:24:52 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00