mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.7 KiB
Python
49 lines
1.7 KiB
Python
from random import Random
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def main():
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r = Random(1)
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N = 750
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with open("tests/arch/gatemate/luttrees.v", "w") as v:
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print(f"module luttrees(input [{N-1}:0] a, b, c, d, e, output [{N-1}:0] q);", file=v)
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for i in range(N):
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def f():
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return r.choice(["&", "|", "^"])
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def a(x):
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return f"({r.choice(['', '!'])}{x}[{i}])"
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# Bias towards testing bigger functions
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k = r.choice([2, 3, 4, 4, 4, 5, 5, 5])
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if k == 2:
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expr = f"{a('a')}{f()}{a('b')}"
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elif k == 3:
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expr = f"({a('a')}{f()}{a('b')}){f()}{a('c')}"
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elif k == 4:
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# Two types of 4-input function
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if r.choice([False, True]):
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expr = f"(({a('a')}{f()}{a('b')}){f()}{a('c')}){f()}{a('d')}"
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else:
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expr = f"({a('a')}{f()}{a('b')}){f()}({a('c')}{f()}{a('d')})"
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elif k == 5:
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expr = f"(({a('a')}{f()}{a('b')}){f()}({a('c')}{f()}{a('d')})){f()}{a('e')}"
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print(f" assign q[{i}] = {expr};", file=v)
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print("endmodule", file=v)
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with open("tests/arch/gatemate/luttrees.ys", "w") as s:
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print(f"""
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read_verilog luttrees.v
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design -save read
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hierarchy -top luttrees
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd luttrees # Constrain all select calls below inside the top module
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select -assert-count {N} t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
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select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
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""", file=s)
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if __name__ == '__main__':
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main()
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