mirror of https://github.com/YosysHQ/yosys.git
14 lines
866 B
Makefile
14 lines
866 B
Makefile
OBJS += techlibs/quicklogic/synth_quicklogic.o
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v))
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$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v))
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