Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic		2019-09-15 09:37:16 +02:00
..
achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Added simulation models for Efinix and Anlogic	2019-09-15 09:37:16 +02:00
common	Use a dummy box file if none specified	2019-08-28 20:58:55 -07:00
coolrunner2	Fix spacing	2019-08-06 16:47:55 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Rename box	2019-09-02 12:15:11 -07:00
efinix	Added simulation models for Efinix and Anlogic	2019-09-15 09:37:16 +02:00
gowin	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-30 10:30:46 -07:00
intel	techlibs/intel: Clean up Makefile	2019-08-05 11:22:11 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	synth_xilinx: Support init values on Spartan 6 flip-flops properly.	2019-09-07 16:30:43 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00