bram $__TRELLIS_DPR16X4
init 1
abits 4
dbits 4
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__TRELLIS_DPR16X4
make_outreg
min wports 1
endmatch