mirror of https://github.com/YosysHQ/yosys.git
72 lines
2.0 KiB
Verilog
72 lines
2.0 KiB
Verilog
`default_nettype none
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module \$alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y, CO;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BX = B_buf;
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wire [Y_WIDTH:0] ALM_CARRY;
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// Start of carry chain
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generate
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if (_TECHMAP_CONSTMSK_CI_ == 1) begin
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assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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end else begin
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // Q = A
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.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
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) alm_start (
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.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
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.CI(1'b0),
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.CO(ALM_CARRY[0])
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);
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end
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endgenerate
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// Carry chain
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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// TODO: mwk suggests that a pass could merge pre-adder logic into this.
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // Q = A
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.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
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) alm_i (
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.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
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.CI(ALM_CARRY[i]),
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.SO(Y[i]),
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.CO(ALM_CARRY[i+1])
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);
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// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
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assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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