mirror of https://github.com/YosysHQ/yosys.git
30 lines
537 B
Verilog
30 lines
537 B
Verilog
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module \$mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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input [A_WIDTH-1:0] A;
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generate if (A_SIGNED) begin:A_BUF
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wire signed [A_WIDTH-1:0] val = A;
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end else begin:A_BUF
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wire [A_WIDTH-1:0] val = A;
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end endgenerate
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input [B_WIDTH-1:0] B;
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generate if (B_SIGNED) begin:B_BUF
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wire signed [B_WIDTH-1:0] val = B;
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end else begin:B_BUF
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wire [B_WIDTH-1:0] val = B;
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end endgenerate
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output [Y_WIDTH-1:0] Y;
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assign Y = A_BUF.val * B_BUF.val;
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endmodule
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