mirror of https://github.com/YosysHQ/yosys.git
23 lines
291 B
Verilog
23 lines
291 B
Verilog
module test(in, out);
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input in;
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output out;
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wire w1, w2, w3, w4;
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assign w1 = in;
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assign w2 = w1;
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assign w4 = w3;
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assign out = w4;
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mybuf _mybuf(w2, w3);
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endmodule
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module mybuf(in, out);
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input in;
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output out;
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wire w1, w2, w3, w4;
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assign w1 = in;
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assign w2 = w1;
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assign out = w2;
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endmodule
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