mirror of https://github.com/YosysHQ/yosys.git
43 lines
1.5 KiB
Plaintext
43 lines
1.5 KiB
Plaintext
read_verilog mux.v
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design -save read
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proc
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hierarchy -top mux2
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT3
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select -assert-none t:AL_MAP_LUT3 %% t:* %D
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design -load read
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proc
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hierarchy -top mux4
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT6
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select -assert-none t:AL_MAP_LUT6 %% t:* %D
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design -load read
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proc
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hierarchy -top mux8
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 3 t:AL_MAP_LUT4
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select -assert-count 1 t:AL_MAP_LUT6
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select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D
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design -load read
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proc
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hierarchy -top mux16
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 5 t:AL_MAP_LUT6
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select -assert-none t:AL_MAP_LUT6 %% t:* %D
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