mirror of https://github.com/YosysHQ/yosys.git
1236bb65b6
Consider this SystemVerilog file:
module top(...);
input clk;
input [7:0] data;
input ack;
always @(posedge clk)
if (ack) begin
assert(data != 8'h0a);
end
endmodule
Before this commit, the span for the assert was:
if (ack) begin>
assert(data != 8'h0a)<;
After this commit, the span for the assert is:
if (ack) begin
>assert(data != 8'h0a)<;
This helps editor integrations that only look at the beginning
of the span.
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| .. | ||
| .gitignore | ||
| Makefile.inc | ||
| const2ast.cc | ||
| preproc.cc | ||
| preproc.h | ||
| verilog_frontend.cc | ||
| verilog_frontend.h | ||
| verilog_lexer.l | ||
| verilog_parser.y | ||