yosys/techlibs
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
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achronix Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
anlogic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
common memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 ecp5: Add DCSC blackbox 2021-07-06 14:07:20 +01:00
efinix Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
gowin Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 ice40: Fix LUT input indices in opt_lut -dlogic (again). 2021-07-10 21:30:01 +02:00
intel Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
intel_alm Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
machxo2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
nexus Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
quicklogic quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
sf2 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
xilinx Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00