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achronix
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Test fixes for latest iverilog
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2022-09-21 15:46:43 +02:00 |
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anlogic
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anlogic: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
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common
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Add bitwise `$bweqx` and `$bwmux` cells
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2022-11-30 18:24:35 +01:00 |
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coolrunner2
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Blackbox all whiteboxes after synthesis
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2021-03-17 21:07:20 +00:00 |
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easic
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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ecp5
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ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
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2023-04-06 10:18:48 +01:00 |
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efinix
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efinix: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
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fabulous
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fabulous: Add support for LUT6s
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2023-04-12 18:42:09 +02:00 |
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gatemate
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gatemate: Enable register initialization
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2023-02-15 17:29:01 +01:00 |
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gowin
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gowin: Fix X output of $alu techmap
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2023-05-01 17:56:41 +02:00 |
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greenpak4
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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ice40
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ice40: Fix path delay definitions
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2023-03-10 10:48:05 +01:00 |
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intel
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Fitting help messages to 80 character width
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2022-08-24 10:40:57 +12:00 |
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intel_alm
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Fitting help messages to 80 character width
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2022-08-24 10:40:57 +12:00 |
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machxo2
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Add PLL and EBR related primitives
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2023-04-10 12:39:09 +02:00 |
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nexus
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nexus: Fix BRAM write enable in PDP mode
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2023-01-04 17:59:36 +01:00 |
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quicklogic
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Fitting help messages to 80 character width
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2022-08-24 10:40:57 +12:00 |
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sf2
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Test fixes for latest iverilog
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2022-09-21 15:46:43 +02:00 |
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xilinx
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Update Xilinx cell definitions, fixes #3699
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2023-03-23 09:44:36 +01:00 |
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.gitignore
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added .gitignore files
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2013-01-05 11:19:11 +01:00 |
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