mirror of https://github.com/YosysHQ/yosys.git
16 lines
373 B
Verilog
16 lines
373 B
Verilog
// Like pack2.v, but results in a simpler network.
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module top(...);
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(* $flowmap_level=1 *) input a;
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(* $flowmap_level=1 *) input b;
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(* $flowmap_level=2 *) input c;
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(* $flowmap_level=1 *) input d;
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(* $flowmap_level=3 *) input e;
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(* $flowmap_level=1 *) input f;
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wire u = a&b;
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wire w = c|d;
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wire v = u|w;
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wire n0 = w&e;
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wire n1 = n0|f;
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output n2 = v&n1;
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endmodule
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