mirror of https://github.com/YosysHQ/yosys.git
19 lines
659 B
Plaintext
19 lines
659 B
Plaintext
read_verilog ../common/fsm.v
|
|
hierarchy -top fsm
|
|
proc
|
|
flatten
|
|
|
|
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
|
|
miter -equiv -make_assert -flatten gold gate miter
|
|
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd fsm # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 1 t:AL_MAP_LUT2
|
|
select -assert-count 5 t:AL_MAP_LUT5
|
|
select -assert-count 1 t:AL_MAP_LUT6
|
|
select -assert-count 6 t:AL_MAP_SEQ
|
|
|
|
select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
|