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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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2fa0fd4a37
yosys
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frontends
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Clifford Wolf
2d32c6c4f6
Fixed handling of local memories in functions
2017-01-05 13:19:03 +01:00
..
ast
Fixed handling of local memories in functions
2017-01-05 13:19:03 +01:00
blif
No limit for length of lines in BLIF front-end
2016-10-19 12:44:58 +02:00
ilang
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
liberty
Added liberty parser support for types within cell decls
2016-09-23 13:53:23 +02:00
verific
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
verilog
Added "verilog_defines" command
2016-12-15 17:49:28 +01:00
vhdl2verilog
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00