mirror of https://github.com/YosysHQ/yosys.git
404 lines
13 KiB
C++
404 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#include "verilog_frontend.h"
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#include "kernel/yosys.h"
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#include "libs/sha1/sha1.h"
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#include <stdarg.h>
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YOSYS_NAMESPACE_BEGIN
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using namespace VERILOG_FRONTEND;
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// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
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static std::vector<std::string> verilog_defaults;
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static std::list<std::vector<std::string>> verilog_defaults_stack;
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_verilog [options] [filename]\n");
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log("\n");
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log("Load modules from a verilog file to the current design. A large subset of\n");
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log("Verilog-2005 is supported.\n");
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log("\n");
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log(" -sv\n");
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log(" enable support for SystemVerilog features. (only a small subset\n");
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log(" of SystemVerilog is supported)\n");
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log("\n");
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log(" -formal\n");
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log(" enable support for assert() and assume() statements\n");
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log(" (assert support is also enabled with -sv)\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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log("\n");
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log(" -dump_ast2\n");
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" dump ast as verilog code (after simplification)\n");
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log("\n");
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log(" -yydebug\n");
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log(" enable parser debug output\n");
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log("\n");
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log(" -nolatches\n");
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log(" usually latches are synthesized into logic loops\n");
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log(" this option prohibits this and sets the output to 'x'\n");
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log(" in what would be the latches hold condition\n");
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log("\n");
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log(" this behavior can also be achieved by setting the\n");
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log(" 'nolatches' attribute on the respective module or\n");
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log(" always block.\n");
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log("\n");
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log(" -nomem2reg\n");
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log(" under certain conditions memories are converted to registers\n");
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log(" early during simplification to ensure correct handling of\n");
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log(" complex corner cases. this option disables this behavior.\n");
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log("\n");
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log(" this can also be achieved by setting the 'nomem2reg'\n");
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log(" attribute on the respective module or register.\n");
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log("\n");
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log(" This is potentially dangerous. Usually the front-end has good\n");
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log(" reasons for converting an array to a list of registers.\n");
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log(" Prohibiting this step will likely result in incorrect synthesis\n");
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log(" results.\n");
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log("\n");
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log(" -mem2reg\n");
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log(" always convert memories to registers. this can also be\n");
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log(" achieved by setting the 'mem2reg' attribute on the respective\n");
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log(" module or register.\n");
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log("\n");
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log(" -nomeminit\n");
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log(" do not infer $meminit cells and instead convert initialized\n");
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log(" memories to registers directly in the front-end.\n");
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log("\n");
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log(" -ppdump\n");
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log(" dump verilog code after pre-processor\n");
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log("\n");
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
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log("\n");
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log(" -noopt\n");
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log(" don't perform basic optimizations (such as const folding) in the\n");
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log(" high-level front-end.\n");
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log("\n");
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log(" -icells\n");
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log(" interpret cell types starting with '$' as internal cell types\n");
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log("\n");
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log(" -ignore_redef\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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log("\n");
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log(" -defer\n");
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log(" only read the abstract syntax tree and defer actual compilation\n");
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log(" to a later 'hierarchy' command. Useful in cases where the default\n");
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log(" parameters of modules yield invalid or not synthesizable code.\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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log(" -Dname[=definition]\n");
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log(" define the preprocessor symbol 'name' and set its optional value\n");
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log(" 'definition'\n");
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log("\n");
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log(" -Idir\n");
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log(" add 'dir' to the directories which are used when searching include\n");
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log(" files\n");
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log("\n");
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log("The command 'verilog_defaults' can be used to register default options for\n");
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log("subsequent calls to 'read_verilog'.\n");
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log("\n");
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log("Note that the Verilog frontend does a pretty good job of processing valid\n");
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log("verilog input, but has not very good error reporting. It generally is\n");
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log("recommended to use a simulator (for example icarus verilog) for checking\n");
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log("the syntax of the code, rather than to rely on read_verilog for that.\n");
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log("\n");
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}
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virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_dump_vlog = false;
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bool flag_nolatches = false;
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bool flag_nomeminit = false;
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bool flag_nomem2reg = false;
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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bool flag_lib = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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bool flag_ignore_redef = false;
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bool flag_defer = false;
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std::map<std::string, std::string> defines_map;
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std::list<std::string> include_dirs;
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std::list<std::string> attributes;
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frontend_verilog_yydebug = false;
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sv_mode = false;
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formal_mode = false;
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log_header("Executing Verilog-2005 frontend.\n");
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args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-sv") {
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sv_mode = true;
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continue;
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}
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if (arg == "-formal") {
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formal_mode = true;
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continue;
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}
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if (arg == "-dump_ast1") {
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flag_dump_ast1 = true;
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continue;
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}
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if (arg == "-dump_ast2") {
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flag_dump_ast2 = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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continue;
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}
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if (arg == "-yydebug") {
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frontend_verilog_yydebug = true;
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continue;
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}
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if (arg == "-nolatches") {
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flag_nolatches = true;
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continue;
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}
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if (arg == "-nomeminit") {
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flag_nomeminit = true;
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continue;
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}
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if (arg == "-nomem2reg") {
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flag_nomem2reg = true;
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continue;
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}
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if (arg == "-mem2reg") {
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flag_mem2reg = true;
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continue;
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}
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if (arg == "-ppdump") {
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flag_ppdump = true;
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continue;
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}
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if (arg == "-nopp") {
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flag_nopp = true;
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continue;
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}
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if (arg == "-lib") {
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flag_lib = true;
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defines_map["BLACKBOX"] = string();
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continue;
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}
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if (arg == "-noopt") {
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flag_noopt = true;
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continue;
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}
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if (arg == "-icells") {
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flag_icells = true;
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continue;
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}
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if (arg == "-ignore_redef") {
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flag_ignore_redef = true;
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continue;
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}
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if (arg == "-defer") {
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flag_defer = true;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (arg == "-D" && argidx+1 < args.size()) {
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std::string name = args[++argidx], value;
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size_t equal = name.find('=', 2);
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if (equal != std::string::npos) {
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value = arg.substr(equal+1);
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name = arg.substr(0, equal);
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}
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defines_map[name] = value;
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continue;
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}
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if (arg.compare(0, 2, "-D") == 0) {
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size_t equal = arg.find('=', 2);
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std::string name = arg.substr(2, equal-2);
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std::string value;
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if (equal != std::string::npos)
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value = arg.substr(equal+1);
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defines_map[name] = value;
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continue;
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}
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if (arg == "-I" && argidx+1 < args.size()) {
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include_dirs.push_back(args[++argidx]);
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continue;
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}
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if (arg.compare(0, 2, "-I") == 0) {
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include_dirs.push_back(arg.substr(2));
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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log("Parsing %s%s input from `%s' to AST representation.\n",
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formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
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AST::current_filename = filename;
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AST::set_line_num = &frontend_verilog_yyset_lineno;
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AST::get_line_num = &frontend_verilog_yyget_lineno;
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current_ast = new AST::AstNode(AST::AST_DESIGN);
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default_nettype_wire = true;
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lexin = f;
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std::string code_after_preproc;
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if (!flag_nopp) {
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code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, include_dirs);
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if (flag_ppdump)
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log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
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lexin = new std::istringstream(code_after_preproc);
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}
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frontend_verilog_yyset_lineno(1);
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frontend_verilog_yyrestart(NULL);
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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for (auto &child : current_ast->children) {
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if (child->type == AST::AST_MODULE)
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for (auto &attr : attributes)
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if (child->attributes.count(attr) == 0)
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child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
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}
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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delete current_ast;
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current_ast = NULL;
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log("Successfully finished Verilog frontend.\n");
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}
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} VerilogFrontend;
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struct VerilogDefaults : public Pass {
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VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" verilog_defaults -add [options]\n");
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log("\n");
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log("Add the sepcified options to the list of default options to read_verilog.\n");
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log("\n");
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log("\n");
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log(" verilog_defaults -clear");
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log("\n");
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log("Clear the list of verilog default options.\n");
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log("\n");
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log("\n");
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log(" verilog_defaults -push");
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log(" verilog_defaults -pop");
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log("\n");
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log("Push or pop the list of default options to a stack. Note that -push does\n");
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log("not imply -clear.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design*)
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{
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if (args.size() == 0)
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cmd_error(args, 1, "Missing argument.");
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if (args[1] == "-add") {
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verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
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return;
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}
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if (args.size() != 2)
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cmd_error(args, 2, "Extra argument.");
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if (args[1] == "-clear") {
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verilog_defaults.clear();
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return;
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}
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if (args[1] == "-push") {
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verilog_defaults_stack.push_back(verilog_defaults);
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return;
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}
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if (args[1] == "-pop") {
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if (verilog_defaults_stack.empty()) {
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verilog_defaults.clear();
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} else {
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verilog_defaults.swap(verilog_defaults_stack.back());
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verilog_defaults_stack.pop_back();
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}
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return;
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}
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}
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} VerilogDefaults;
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YOSYS_NAMESPACE_END
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// the yyerror function used by bison to report parser errors
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void frontend_verilog_yyerror(char const *fmt, ...)
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{
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va_list ap;
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char buffer[1024];
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char *p = buffer;
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p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
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YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
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va_start(ap, fmt);
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p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
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va_end(ap);
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p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
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YOSYS_NAMESPACE_PREFIX log_error("%s", buffer);
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exit(1);
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}
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