Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection ... The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().		2021-06-08 15:03:16 -04:00
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aiger	Provide an integer implementation of decimal_digits().	2021-02-01 11:23:44 -08:00
ast	verilog: check for module scope identifiers during width detection	2021-06-08 15:03:16 -04:00
blif	blif: Use library cells' start_offset and upto for wideports.	2021-05-08 15:50:03 +02:00
json	Remove duplicates from conns array in JSON front-end, fixes #2736	2021-04-26 16:32:12 +02:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	Add support for memory writes in processes.	2021-03-08 20:16:29 +01:00
verific	Update README	2021-03-04 16:43:30 +01:00
verilog	sv: support tasks and functions within packages	2021-06-01 13:17:41 -04:00