mirror of https://github.com/YosysHQ/yosys.git
54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
module \$_DFF_P_ (D, C, Q);
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input D, C;
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output Q;
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FDRE fpga_dff (
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.D(D), .Q(Q), .C(C),
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.CE(1'b1), .R(1'b0)
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin:lut1
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LUT1 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]));
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end else
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if (WIDTH == 2) begin:lut2
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LUT2 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]), .I1(A[1]));
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end else
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if (WIDTH == 3) begin:lut3
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LUT3 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]));
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end else
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if (WIDTH == 4) begin:lut4
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LUT4 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]));
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end else
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if (WIDTH == 5) begin:lut5
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LUT5 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]));
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end else
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if (WIDTH == 6) begin:lut6
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LUT6 #(.INIT(LUT)) fpga_lut (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]),
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.I3(A[3]), .I4(A[4]), .I5(A[5]));
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end else begin:error
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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