mirror of https://github.com/YosysHQ/yosys.git
457 lines
12 KiB
Python
457 lines
12 KiB
Python
TEMPLATES = [
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SR_{S:N|P}{R:N|P}_ (S, R, Q)
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//* group reg_latch
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//-
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//- A set-reset latch with {S:negative|positive} polarity SET and {R:negative|positive} polarity RESET.
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//-
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//- Truth table: S R | Q
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//- -----+---
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//- - {R:0|1} | 0
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//- {S:0|1} - | 1
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//- - - | q
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//-
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module \$_SR_{S:N|P}{R:N|P}_ (S, R, Q);
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input S, R;
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output reg Q;
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always @* begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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end
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endmodule
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""",
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"""
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`ifdef SIMCELLS_FF
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_FF_ (D, Q)
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//* group reg_ff
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//-
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//- A D-type flip-flop that is clocked from the implicit global clock. (This cell
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//- type is usually only used in netlists for formal verification.)
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//-
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module \$_FF_ (D, Q);
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input D;
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output reg Q;
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always @($global_clock) begin
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Q <= D;
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end
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endmodule
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`endif
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFF_{C:N|P}_ (D, C, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop.
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//-
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//- Truth table: D C | Q
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//- -----+---
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//- d {C:\\|/} | d
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//- - - | q
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//-
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module \$_DFF_{C:N|P}_ (D, C, Q);
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input D, C;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {E:negative|positive} polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d {C:\\|/} {E:0|1} | d
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//- - - - | q
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//-
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module \$_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q);
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input D, C, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if ({E:!E|E}) Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set}.
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//-
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//- Truth table: D C R | Q
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//- -------+---
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//- - - {R:0|1} | {V:0|1}
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//- d {C:\\|/} - | d
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//- - - - | q
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//-
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module \$_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
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input D, C, R;
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output reg Q;
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always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
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//- polarity clock enable.
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - - {R:0|1} - | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_ALDFF_{C:N|P}{L:N|P}_ (D, C, L, AD, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {L:negative|positive} polarity async load.
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//-
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//- Truth table: D C L AD | Q
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//- ----------+---
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//- - - {L:0|1} a | a
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//- d {C:\\|/} - - | d
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//- - - - - | q
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//-
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module \$_ALDFF_{C:N|P}{L:N|P}_ (D, C, L, AD, Q);
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input D, C, L, AD;
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output reg Q;
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always @({C:neg|pos}edge C or {L:neg|pos}edge L) begin
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if (L == {L:0|1})
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Q <= AD;
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_ALDFFE_{C:N|P}{L:N|P}{E:N|P}_ (D, C, L, AD, E, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {L:negative|positive} polarity async load and {E:negative|positive}
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//- polarity clock enable.
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//-
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//- Truth table: D C L AD E | Q
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//- ------------+---
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//- - - {L:0|1} a - | a
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//- d {C:\\|/} - - {E:0|1} | d
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//- - - - - - | q
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//-
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module \$_ALDFFE_{C:N|P}{L:N|P}{E:N|P}_ (D, C, L, AD, E, Q);
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input D, C, L, AD, E;
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output reg Q;
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always @({C:neg|pos}edge C or {L:neg|pos}edge L) begin
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if (L == {L:0|1})
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Q <= AD;
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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//- - - {R:0|1} - | 0
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//- - {S:0|1} - - | 1
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//- {C:\\|/} - - d | d
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//- - - - - | q
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//-
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module \$_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q);
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input C, S, R, D;
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output reg Q;
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always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
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//- polarity reset and {E:negative|positive} polarity clock enable.
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//-
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//- Truth table: C S R E D | Q
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//- -----------+---
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//- - - {R:0|1} - - | 0
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//- - {S:0|1} - - - | 1
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//- {C:\\|/} - - {E:0|1} d | d
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//- - - - - - | q
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//-
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module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
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input C, S, R, E, D;
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output reg Q;
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always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
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//-
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//- Truth table: D C R | Q
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//- -------+---
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//- - {C:\\|/} {R:0|1} | {V:0|1}
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//- d {C:\\|/} - | d
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//- - - - | q
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//-
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module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
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input D, C, R;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
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//- polarity clock enable (with {V:reset|set} having priority).
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - {C:\\|/} {R:0|1} - | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//* group reg_ff
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
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//- polarity clock enable (with clock enable having priority).
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (E == {E:0|1}) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCH_{E:N|P}_ (E, D, Q)
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//* group reg_latch
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//-
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//- A {E:negative|positive} enable D-type latch.
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//-
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//- Truth table: E D | Q
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//- -----+---
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//- {E:0|1} d | d
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//- - - | q
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//-
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module \$_DLATCH_{E:N|P}_ (E, D, Q);
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input E, D;
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output reg Q;
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always @* begin
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if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
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//* group reg_latch
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//-
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//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
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//-
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//- Truth table: E R D | Q
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//- -------+---
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//- - {R:0|1} - | {V:0|1}
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//- {E:0|1} - d | d
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//- - - - | q
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//-
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module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
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//* group reg_latch
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//-
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//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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//- - - {R:0|1} - | 0
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//- - {S:0|1} - - | 1
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//- {E:0|1} - - d | d
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//- - - - - | q
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//-
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module \$_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q);
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input E, S, R, D;
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output reg Q;
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always @* begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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]
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lines = []
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with open('simcells.v') as f:
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for l in f:
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lines.append(l)
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if 'START AUTOGENERATED CELL TYPES' in l:
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break
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with open('simcells.v', 'w') as f:
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for l in lines:
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f.write(l)
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for template in TEMPLATES:
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chunks = []
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vars = {}
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pos = 0
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while pos < len(template):
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if template[pos] != '{':
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np = template.find('{', pos)
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if np == -1:
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np = len(template)
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chunks.append(template[pos:np])
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pos = np
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else:
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np = template.index('}', pos)
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sub = template[pos + 1:np]
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pos = np + 1
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var, _, vals = sub.partition(':')
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if not vals:
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raise ValueError(sub)
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vals = vals.split('|')
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if var not in vars:
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vars[var] = len(vals)
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else:
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if vars[var] != len(vals):
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raise ValueError(vars[var], vals)
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chunks.append((var, vals))
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combs = [{}]
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for var in vars:
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combs = [
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{
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var: i,
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**comb,
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}
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for comb in combs
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for i in range(vars[var])
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]
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for comb in combs:
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f.write(
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''.join(
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c if isinstance(c, str) else c[1][comb[c[0]]]
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for c in chunks
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)
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)
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