yosys/frontends
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
..
aiger aiger: -xaiger to return $_FF_ flops 2020-05-14 10:33:56 -07:00
ast Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 2020-05-14 18:06:18 +02:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
ilang frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
rpc Add WASI platform support. 2020-04-30 18:56:25 +00:00
verific Revert "Add support for non-power-of-two mem chunks in verific importer" 2020-05-17 11:31:11 +02:00
verilog verilog: default to input in sv mode if task/func has no dir ... 2020-05-13 13:33:37 -07:00