mirror of https://github.com/YosysHQ/yosys.git
98 lines
2.6 KiB
TeX
98 lines
2.6 KiB
TeX
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\section{Introduction}
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\begin{frame}
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\sectionpage
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Representations of (digital) Circuits}
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\begin{frame}[t]{\subsecname}
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\begin{itemize}
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\item Graphical
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\begin{itemize}
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\item \alert<1>{Schematic Diagram}
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\item \alert<2>{Physical Layout}
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\end{itemize}
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\bigskip
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\item Non-graphical
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\begin{itemize}
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\item \alert<3>{Netlists}
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\item \alert<4>{Hardware Description Languages (HDLs)}
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\end{itemize}
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\end{itemize}
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\bigskip
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\begin{block}{Definition:
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\only<1>{Schematic Diagram}%
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\only<2>{Physical Layout}%
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\only<3>{Netlists}%
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\only<4>{Hardware Description Languages (HDLs)}}
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\only<1>{TBD}
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\only<2>{TBD}
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\only<3>{TBD}
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\only<4>{TBD}
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\end{block}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Levels of Abstraction for Digital Circuits}
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\begin{frame}[t]{\subsecname}
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\begin{itemize}
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\item \alert<1>{System Level}
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\item \alert<2>{High Level}
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\item \alert<3>{Behavioral Level}
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\item \alert<4>{Register-Transfer Level (RTL)}
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\item \alert<5>{Logical Gate Level}
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\item \alert<6>{Physical Gate Level}
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\item \alert<7>{Switch Level}
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\end{itemize}
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\bigskip
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\begin{block}{Definition:
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\only<1>{System Level}%
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\only<2>{High Level}%
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\only<3>{Behavioral Level}%
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\only<4>{Register-Transfer Level (RTL)}%
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\only<5>{Logical Gate Level}%
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\only<6>{Physical Gate Level}%
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\only<7>{Switch Level}}
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\only<1>{
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Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
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}%
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\only<2>{
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Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
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}%
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\only<3>{
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Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
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}%
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\only<4>{
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List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
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a netlist utilizing high-level cells such as adders, multiplieres, multiplexer, etc.
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}%
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\only<5>{
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Netlist of single-bit registers and basic logic gates (such as AND, OR,
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NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
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inputs and outputs for each register bit.
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}%
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\only<6>{
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Netlist of cells that actually are available on the target architecture
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(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
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area and/or and/or speed (static timing or number of logic levels).
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}%
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\only<7>{
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Netlist of individual transistors.
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}%
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\end{block}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Digital Circuit Synthesis}
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\begin{frame}{\subsecname}
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\end{frame}
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