mirror of https://github.com/YosysHQ/yosys.git
16 lines
320 B
Tcl
16 lines
320 B
Tcl
yosys -import
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read_verilog +/choices/han-carlson.v
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read_verilog -icells lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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opt_clean
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equiv_make lcu _80_lcu_han_carlson equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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