mirror of https://github.com/YosysHQ/yosys.git
12 lines
459 B
Plaintext
12 lines
459 B
Plaintext
read_verilog mul_unsigned.v
|
|
proc
|
|
hierarchy -top mul_unsigned
|
|
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mul_unsigned # Constrain all select calls below inside the top module
|
|
stat
|
|
select -assert-count 1 t:BUFG
|
|
select -assert-count 1 t:DSP48E1
|
|
select -assert-count 30 t:FDRE
|
|
select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D
|