mirror of https://github.com/YosysHQ/yosys.git
120 lines
3.7 KiB
C++
120 lines
3.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static std::string hicell_celltype, hicell_portname;
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static std::string locell_celltype, locell_portname;
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static bool singleton_mode;
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static RTLIL::Module *module;
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static RTLIL::SigBit last_hi, last_lo;
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void hilomap_worker(RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig) {
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if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
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if (!singleton_mode || last_hi == RTLIL::State::Sm) {
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last_hi = module->addWire(NEW_ID);
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
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cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
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}
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bit = last_hi;
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}
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if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
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if (!singleton_mode || last_lo == RTLIL::State::Sm) {
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last_lo = module->addWire(NEW_ID);
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
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cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
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}
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bit = last_lo;
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}
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}
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}
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struct HilomapPass : public Pass {
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HilomapPass() : Pass("hilomap", "technology mapping of constant hi- and/or lo-drivers") { }
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void help() override
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{
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log("\n");
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log(" hilomap [options] [selection]\n");
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log("\n");
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log("Map constants to 'tielo' and 'tiehi' driver cells.\n");
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log("\n");
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log(" -hicell <celltype> <portname>\n");
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log(" Replace constant hi bits with this cell.\n");
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log("\n");
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log(" -locell <celltype> <portname>\n");
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log(" Replace constant lo bits with this cell.\n");
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log("\n");
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log(" -singleton\n");
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log(" Create only one hi/lo cell and connect all constant bits\n");
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log(" to that cell. Per default a separate cell is created for\n");
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log(" each constant bit.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
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hicell_celltype = std::string();
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hicell_portname = std::string();
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locell_celltype = std::string();
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locell_portname = std::string();
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singleton_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-hicell" && argidx+2 < args.size()) {
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hicell_celltype = args[++argidx];
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hicell_portname = args[++argidx];
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continue;
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}
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if (args[argidx] == "-locell" && argidx+2 < args.size()) {
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locell_celltype = args[++argidx];
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locell_portname = args[++argidx];
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continue;
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}
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if (args[argidx] == "-singleton") {
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singleton_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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{
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module = mod;
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last_hi = RTLIL::State::Sm;
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last_lo = RTLIL::State::Sm;
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module->rewrite_sigspecs(hilomap_worker);
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}
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}
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} HilomapPass;
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PRIVATE_NAMESPACE_END
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