This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
2a744b4b82
yosys
/
docs
/
source
/
code_examples
/
techmap
/
mymul_test.v
5 lines
83 B
Verilog
Raw
Blame
History
module
test
(
A
,
B
,
Y
)
;
input
[
1
:
0
]
A
,
B
;
output
[
1
:
0
]
Y
=
A
*
B
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink